The trend in semiconductor technology to double the functional complexity of its products every 18 months (Moore's “law”), which is still valid today after having dominated the industry for the last three decades, has several implicit consequences. First, the cost per functional unit should drop with each generation of complexity so that the cost of the product with its doubled functionality would increase only slightly. Second, the higher product complexity should largely be achieved by shrinking the feature sizes of the chip components while holding the package dimensions constant; preferably, even the packages should shrink. Third, the increased functional complexity should be paralleled by an equivalent increase in reliability of the product. And fourth, but not least, the best financial profit rewards were held out for the ones who were ahead in the marketplace in reaching the complexity goal together with offering the most flexible products for application.
The scaling of the components in the lateral dimension requires vertical scaling as well so as to achieve adequate device performance. This vertical scaling requires the thickness of the gate dielectric, commonly silicon dioxide (SiO2) to be reduced. Thinning of the gate dielectric provides a smaller barrier to dopant diffusion from a polysilicon gate structure (or metal diffusion from a metal gate structure) through the underlying dielectric, often resulting in devices with diminished electrical performance and reliability. In ultra-thin dielectric layers, interfaces with their unwelcome electronic states and carrier traps may finally dominate the electrical characteristics.
One way of reducing these problems is to use silicon nitride as the gate dielectric layer instead of silicon dioxide. Silicon nitride has a higher dielectric constant than typical thermally grown SiO2 and provides greater resistance to impurity diffusion. However, the electrical properties of standard deposited silicon nitride films are far inferior to thermal oxides. One approach for silicon nitride films as gate insulators employs an oxide layer between the nitride layer and the substrate. Unfortunately, this technique has numerous practical shortcomings.
Another approach of maintaining the benefit of the electrical properties of the oxide film while also getting the barrier properties of a nitride film is to incorporate nitrogen into a gate oxide layer. In known technology, this is accomplished by a nitrided oxide process involving ammonia to penetrate the gate oxide at temperatures in excess of 1000° C. Once the high temperature reaction has begun, it is difficult to control the concentration of the nitrogen incorporated into the gate oxide. Excessive nitrogen near the interface between the semiconductor substrate and the gate oxide can adversely affect the threshold voltage and degrade the channel mobility of the device due to charged interface traps associated with the nitrogen.
As described by S. V. Hattangady et al., “Controlled Nitrogen Incorporation at the Gate Oxide Surface,” Appl. Phys. Lett. vol. 66. p. 3495, 1995, a high pressure and low power process provides nitrogen incorporation specifically at the gate/conductor interface. The long exposure time to the plasma increases the probability of charge-induced damage to the oxide and reduces the production throughput.
In U.S. Pat. No. 6,136,654, issued on Oct. 24, 2000 (Kraft et al., “Method of Forming Thin Silicon Nitride or Silicon Oxynitride Gate Dielectrics”), the SiO2 (or oxynitride) layer is subjected to a nitrogen containing plasma so that the nitrogen is either incorporated into the SiO2 layer or forms a nitride layer at the surface of the substrate. The source of nitrogen in the plasma comprises a material consisting of N2, NH3, NO, N2O, or mixtures thereof. This method provides a non-uniform nitrogen distribution in the SiO2 layer and is applicable to relatively thick oxide layers (2 to 15 nm), however, it is not suitable for ultra-thin SiO2 layers (0.5 to 2 nm).
An urgent need has, therefore, arisen for a coherent, low-cost method of plasma nitridation of ultra-thin gate oxide layers. The method should further produce excellent electrical device performance, mechanical stability and high reliability. The fabrication method should be simple, yet flexible enough for different semiconductor product families and a wide spectrum of design and process variations. Preferably, these innovations should be accomplished without extending production cycle time, and using the installed equipment, so that no investment in new manufacturing machines is needed.